1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor integrated circuit having a stacked package structure.
2. Description of the Related Art
In general, a packaging technology of a semiconductor integrated circuit has been developed to satisfy minimization and mounting reliability thereof. Recently, various technologies for a stacked package have been developed in order to realize a high performance and minimization of electric/electronic products.
The “stack” structure in a semiconductor industry represents that at least two semiconductor chips or packages are vertically laminated. For example, a semiconductor memory device may be implemented to have a memory capacitance two times more than a memory capacitance implemented during a semiconductor integrated process. Moreover, since stacked packages may have advantages in view of the increase in a memory capacitance and the efficiency of a mounting density and a mounting area, a research and development for the stacked packages have been accelerated.
The stacked package may be fabricated by a method for packaging stacked semiconductor chips at once after semiconductor chips are individually stacked and a method for stacking packaged individual semiconductor chips. The individual semiconductor chips of the stacked package are electrically coupled to each other through a metal wire or a through-chip-via, e.g., through-silicon-via (TSV). Especially, a stacked package using a TSV electrically and physically couples semiconductor chips to each other vertically by forming the TSV in the semiconductor chips.
FIG. 1 is a block diagram illustrating a conventional semiconductor integrated circuit.
Referring to FIG. 1, a semiconductor integrated circuit 100 includes first to fourth semiconductor chips 110 to 140, first to fourth TSVs TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23 and TSV30 to TSV33, and first to fourth bump pads BP00 to BP03, BP10 to BP13, BP20 to BP23 and BP30 to BP33.
The first to fourth semiconductor chips 110 to 140 are vertically stacked, and include first to fourth internal circuits 111 to 117, 121 to 127, 131 to 137 and 141 to 147, which are coupled to the first to fourth TSVs TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23 and TSV30 to TSV33, respectively.
The first to fourth TSVs TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23 and TSV30 to TSV33 penetrate vertically the first to fourth semiconductor chips 110 to 140, and are arranged at a same line in each of the first to fourth semiconductor chips 110 to 140. The first to fourth TSVs TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23 and TSV30 to TSV33 are vertically coupled to each other between the first to fourth semiconductor chips 110 to 140. That is, the first TSVs TSV00, TSV10, TSV20 and TSV30 are vertically coupled to each other. The second TSVs TSV01, TSV11, TSV21 and TSV31 are vertically coupled to each other. The third TSVs TSV02, TSV12, TSV22 and TSV32 are vertically coupled to each other. The fourth TSVs TSV03, TSV13, TSV23 and TSV33 are vertically coupled to each other.
The first to fourth internal circuits 111 to 117, 121 to 127, 131 to 137 and 141 to 147 may include an input/output circuit, respectively.
The memory capacitance of the semiconductor integrated circuit 100 increases as the number of stacked semiconductor chips increases.
However, since the first to fourth TSVs TSV00 to TSV03, TSV10 to TSV13, TSV20 to TSV23 and TSV30 to TSV33 have a common coupling node, the first to fourth semiconductor chips 110 to 140 may receive signals simultaneously but may not output the signals simultaneously. Thus, the semiconductor integrated circuit 100 has a fixed bandwidth although the number of the stacked semiconductor chips increases.
Meanwhile, it is possible to increase a bandwidth by increasing the number of TSVs, which penetrate the first to fourth semiconductor chips 110 to 140, respectively. However, in such a case, since the first to fourth internal circuits 111 to 117, 121 to 127, 131 to 137 and 141 to 147 are additionally disposed in the first to fourth semiconductor chips 110 to 140, an area of the semiconductor chips increases.